8-Bit Computer: Clock Module with Breakpoints

Every 8-bit computer needs a clock module and here is mine.  It is heavily influenced by the Ben Eater clock module, but with some changes.  Firstly, what's the same?  The clock features two 555 clocks, one clock uses an astable 555 configuration and the second clock uses a monostable configuration for single clock stepping.  A third 555 implements a bistable configuration which acts as a selector between the two clocks.  I didn't have a SPDT switch, so used two push buttons instead, which works fine.  The circuitry for the 555s are shown on the top line of the circuit diagram at the bottom of the post.

So what's different with my implementation of this clock module?  Firstly, regarding the logic for clock selection. I replaced the AND, OR and NOT logic gates that Ben uses with just NAND logic gates.  This was driven by a desire to use fewer ICs and because I didn't have any OR chips to hand!  In fact, if you just want to select between the clock source without a HALT signal, you can use four NAND gates, which if you use the 74LS00 that has four on it, means you can implement all the logic with a single IC!  Regarding implementing a HALT signal to bring the computer to an inert halt, I decided instead to have a way of overriding the HALT signal using a button press - in this way, the HALT signal becomes more of a BREAK signal and the CPU can then be resumed by a button press, which will mean that I can have set break-points in the code!

Circuit diagram 

Briefly, a "clock enable" (CLK_EN) signal is used to allow the clock to tick, or not to tick. This control signal in turn is composed from a NAND gate, taking the BREAK signal and a 'continue' signal linked to a button as inputs.  The 'continue' signal is pulled high, and therefore in the case of BREAK being asserted (active high), the control signal CLK_EN goes low, turning off the clock.  If the 'continue' button is pushed when the clock is stopped, 'continue' goes low, CLK_EN goes high, resuming the clock.   The BREAK signal will then be cleared by the control logic by virtue of stepping into the next instruction.